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Aug 29, 2018
Products & Solutions / Blog Posts
Osaka, Japan - Panasonic Corporation announced that it has commercialized a granular semiconductor encapsulation material designed specifically for fan-out wafer-level package (FOWLP(*1)) and panel level packaging (PLP(*2)). Sample production is scheduled to start in September 2018. These new products will increase the productivity of these leading-edge semiconductor packages for wearable and mobile devices and reduce their manufacturing costs.
Electronic designers and manufacturers are increasingly incorporating more functionality into smaller form-factor products. This trend has driven the development and adoption of semiconductor packaging technologies that deliver lower profile, reduced footprint packages using cost-effective and scalable processes. PLP offers the promise of significantly reduced costs because of the large number of semiconductors that can be packaged in each molded panel. Encapsulation materials of these semiconductor packages need to uniformly encapsulate large-area formats like wafers and panels without warpage while exhibiting excellent adhesion to the other structures within the package. The newly commercialized granular epoxy mold compounds meet these requirements.
Panasonic has developed a portfolio of semiconductor encapsulation materials for FOWLP and PLP. In addition to the newly commercialized granular epoxy mold compounds, Panasonic also offers sheet-format encapsulants (suitable for encapsulation thicknesses of 200 μm or less), as well as liquid encapsulation products.
Leading-edge semiconductor packages (FOWLP, PLP, FOSiP (*4), WLCSP (*5), etc.) for radio frequency (RF) and power management ICs used in wearable electronics, mobile devices and other high functionality electronic devices. Series X851C is designed for chip-first packages and X851D is designed for chip-last package.
These new products will be on display in the Panasonic Electronic Materials booth at SEMICON Taiwan 2018, which will be held at the Taipei Nangong Exhibition Center from September 5 to 7, 2018.
1. By combining low warpage with high flow, this material improves the semiconductor packaging process productivity.
Minimizing large-area warpage of molded wafers and panels is important because subsequent processes like sawing and solderball attach require a high degree of planar accuracy. By leveraging Panasonic's unique low-shrinkage and low-stress material formulation expertise, these new products have achieved low warpage without sacrificing flow properties, thereby contributing to improved semiconductor packaging process productivity gains.
2. Excellent wettability to the redistribution layer (RDL) is integral to enabling a package reliability.
Interfacial adhesion between the polyimide insulation layer and the encapsulation material is required to achieve industry-standard reliability performance for chip first package constructions. Through the use of Panasonic's unique resin design technology, these products are designed to bond well to polyimide.
*1: Fan-out wafer-level package (FOWLP)
A package form that enables the formation of package sizes larger than those of IC chips.
*2: Panel level packaging (PLP)
A package manufacturing method that collectively molds a number of chips on a large thin square panel. It usually uses panels larger than 300 mm square for molding and is drawing attention as a high-volume and high-efficiency production method.
*3: Redistribution layer (RDL)
A metal circuit layer for connection to the outside formed on the IC chip.
*4: Fan-out system-in package (FOSiP)
A type of FOWLP package that contains multiple IC chips within a single package.
*5: Wafer-level chip-scale package (WLCSP)
A conventional package form that features its IC chip and package outline as completely the same size.
*6: Chip-first method
A FOWLP manufacturing method that encapsulates IC chips first and subsequently forms the redistribution layers.
*7: Chip-last method
A FOWLP manufacturing method that forms wiring layers first and then encapsulates IC chips.
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